Computer Organization and Architecture: Designing for Performance - 6th Edition (Refer to 0130493074 for International Paperback Edition)
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PRENTICE HALL,June 2002
ENGINEERING Level: I/A
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This book provides a clear, comprehensive presentation of the latest developments in the organization and architecture of modern-day computers, emphasizing both fundamental principles and the critical role of performance in driving computer design. A basic reference and companion for self-study, it conveys concepts through a wealth of concrete examples highlighting modern CISC and RISC systems. KEY TOPICS: A five-part organization covers: an overview, the computer system, the central processing unit, the control unit, and parallel organization. MARKET: For computer engineers and architects, product marketing personnel in computer or communications companies, and for information systems and computer systems personnel.
NEW--Expanded and current coverage of innovations and improvements in the field.
Keeps students up-to-date with the latest technology and captures the rapid pace of change that characterizes the industry.
NEW--An entire chapter devoted to cache memory--(Ch. 4).
Explores a central element in the design of high-performance processors, as well as the complex and important topic of cache design.
Added chapter on IA-64/Itanium architecture--Describes and analyzes the underlying principles of predicated execution and speculative loading.
Familiarizes students with recent concepts central to the design of the new architecture from Intel and Hewlett-Packard.
NEW--Expanded and updated chapter on parallel organization--Covers SMPs, clusters, and NUMA systems descriptions.
Allows students to make detailed comparisons among symmetric multiprocessors (SMPs), clusters, and non-uniform memory access (NUMA) systems.
NEW--Expanded optical memory coverage.
Gives students updated information on magneto-optical memory devices and more.
NEW--Improved illustrations--Features figures and tables.
Clarifies content and concepts throughout the text.
Unique Superscalar design chapter--(Ch. 14).
Introduces students to an approach that dominates the microprocessor design field, including the widely used Pentium.
Unified, complete coverage of instruction set architecture--With rich set of examples (Chs. 10 & 11).
Explains why certain design features are chosen, and enables students to evaluate instruction set design issues.
Detailed treatment of bus organization and specifications--Includes the important examples of PCI and Futurebus+.
Focuses students on the functioning of buses around which virtually all microprocessors are organized, and enables them to evaluate key design issues.
Interaction of I/O modules with the outside world and the CPU--Includes important external interface examples of SCSI and FireWire.
Demonstrates the function and structure of I/O so that students gain a complete understanding of the subject.
Broad presentation of RISC technology.
Unifies important design features found in almost all contemporary machines, including Pentium II and III.
Unified treatment of internal and external memory--Covers leading-edge areas such as magneto-optical; advanced DRAM; and RAID disk arrays.
Enhances students' understanding of hierarchy elements, from cache to optical memory.
Numerous running examples--Especially Pentium 4 and PowerPC G4.
Illustrates systems that encompass many of the contemporary design initiatives.
Full treatment of microprogrammed implementation--Not usually covered in other texts.
Gives students a firm grasp on this area so that they can truly understand processor organization.
Approximately 200 homework problems--With a range of difficulty.
Provides students with the opportunity to test and expand their understanding of chapter material.
Chapter-end review questions.
Ensures students have read and absorbed key content before moving on.
Chapter-end recommended websites and reading lists.
Encourages students to obtain additional and advanced information on subjects discussed in the text.
Up-to-date coverage of EPIC.
Familiarizes students with another modern architectural approach--this one seen in the IA-64 architecture of Intel's Itanium.
Thorough coverage of computer arithmetic--(Ch. 9).
Teaches student twos complement and floating point representations and arithmetic, with detailed examination of IEEE 754.
Table of Contents
2. Computer Evolution and Performance.
II. THE COMPUTER SYSTEM.
3. System Buses.
4. Cache Memory.
5. Internal Memory Technology.
6. External Memory.
8. Operating System Support.
III. THE CENTRAL PROCESSING UNIT.
9. Computer Arithmetic.
10. Instruction Sets: Characteristics and Functions.
11. Instruction Sets: Addressing Modes and Formats.
12. CPU Structure and Function.
13. Reduced Instruction Set Computers (RISCs).
14. Instruction-Level Parallelism and Superscalar Processors.
15. The IA-64 Architecture.
IV. THE CONTROL UNIT.
16. Control Unit Operation.
17. Microprogrammed Control.
V. PARALLEL ORGANIZATION.
18. Parallel Processing.
Appendix A: Digital Logic.
Appendix B: Number Systems
Appendix C: Projects for Teaching Computer Organization and Architecture.